Cache coherence.md (3068B)
1 +++ 2 title = 'Cache coherence' 3 +++ 4 # Cache coherence 5 copies of shared data may be in several caches 6 7 when any processor writes to a shared variable its cache, other caches with a copy of that variable have to be informed of the change — cache coherence 8 9 whenever a block is in a shared state, the memory owns it 10 11 ## Write-through protocol 12 two ways: 13 14 - update protocol — broadcast written data to caches of all processors in the system, each processor updates contents of affected cache 15 - invalidation protocol — broadcast invalidation requests to all processors in the system 16 17 ## Write-back protocol 18 based on concept of ownership of a block of data in the memory 19 20 creates less traffic because writes only happen in cache (unlike write-through) 21 22 - at the start, memory owns all blocks and retains ownership if a block is read 23 - writing to a new block: 24 - the requesting processor must become an exclusive owner of the block 25 - all copies must be invalidated with a broadcast request 26 - reading a modified block 27 - it’s sent by the current owner to the processor and the memory, ending up with two copies in two caches and the memory 28 - subsequent requests for the same block are serviced by the memory module. 29 - writing to a modified block 30 - current owner sends data to requesting processor, which becomes owner 31 - old owner invalidates its cached copy 32 - contents of memory are *not* updated, next request for the block is serviced by the new owner 33 34 ## Snoopy caches 35 all transactions in a single-bus system occur through requests/responses on bus 36 37 snooping is observing all transactions on the bus through a controller circuit 38 39 if a processor broadcasts a read request for a block owned by a processor, the memory is not allowed to respond 40 41 the owner of the block snoops on the bus and sees the request, and asserts a signal on the bus that effectively tells the memory “hell nah bitch I got this” 42 43 then the owner broadcasts a copy of the block on the bus, marks its copy as unmodified, and the response is accepted by the processor that issued the read request. 44 45 the memory also reacquires ownership of the block and updates its copy (and its shared because there’s two copies in caches of two processors) 46 47 further requests are serviced by the memory. 48 49 if two processors have copies and both try to write to the same cache at the same time: 50 51 1. One of the processors gets to use the bus first, broadcasts an invalidation request, and becomes the owner 52 53 2. The other processor snoops and invalidates its copy 54 55 3. When other processor gets to use the bus, it broadcasts a read-exclusive request (read + invalidation request) 56 57 4. Owner snoops the read-exclusive request, provides a data response, and invalidates its copy (other processor becomes new owner) 58 59 an alternative in large shared-memory multiprocessors is directory-based cache coherence, where there are directories in each memory module which indicate which nodes can have copies of a given block 60 61 if a block is modified, the directory identifies node that is current owner